`ifndef ROM_V
`define ROM_V


`include "../core/defines.v"

module rom(
	input  wire                     clk,
    input  wire                     rstn,
    input  wire                     wen,
    input  wire[31 : 0] 			waddr_i,
    input  wire[31 : 0] 			wdata_i,
    input  wire                     ren,
    input  wire[31 : 0] 			raddr_i,
    output reg[31 : 0]  			rdata_o
);

wire[11:0] waddr_wire = waddr_i[13:2];
wire[11:0] raddr_wire = raddr_i[13:2];

dual_ram #(
    .DATA_WIDTH (32),
    .ADDR_WIDTH (12),
    .MEM_NUM    (4096)
) u_dual_ram(
    .clk        (clk),
    .rstn       (rstn),
    .wen        (wen),
    .waddr_i    (waddr_wire),
    .wdata_i    (wdata_i),
    .ren        (ren),
    .raddr_i    (raddr_wire),
    .rdata_o    (rdata_o)
);

endmodule


`endif // ROM_V